Fully depleted silicon-on-insulator (FDSOI) is a CMOS technology with many attractive features. Primary among these are low off-state current due to better electrostatics and also the capability for low-power operation due to low local-variation and mismatch in FDSOI technologies.
Conventional methods of determining a FDSOI thickness are, generally, optical methods using ellipsometry and measurement of transistor characteristics.
Methods based upon optics have very low throughput and allow only a small sample of sites on a wafer to be measured in a reasonable time.
Methods based on measuring transistor characteristics such as line threshold voltage (Vth) and having a separate model which maps Tsi to Vth exist, with the difficulty being that an electrical parameter like Vth is sensitive to many factors like gate length, width, gate dielectric thickness, work-function etc. Extracting Tsi from a Vth measurement requires separating the impact of each of these factors, which is very difficult in practice.